1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for manufacturing shallow trench isolation (STI).
2. Description of Related Art
A complete integrated circuit is generally made from tens of thousands of transistors. To prevent the short-circuiting of any two neighboring transistors, an insulating layer is normally formed between the transistors for isolating the devices. For example, shallow trench isolation is formed by etching a trench in the substrate and then filling the trench with an insulating material to define an active device area.
FIGS. 1A through 1C are cross-sections showing the progression of manufacturing steps in the production of conventional shallow trench isolation. First, as shown in FIG. 1A, a substrate 10 is provided. Then, a pad oxide layer 11 is formed over the substrate 10 using a thermal oxidation process. The pad oxide layer can be, for example, a silicon dioxide layer. Thereafter, a silicon nitride layer 12 (Si.sub.3 N.sub.4) is formed over the pad oxide layer 11 using a low pressure chemical vapor deposition (LPCVD) method.
Next, as shown in FIG. 1B, a photoresist layer 13 is formed over the silicon nitride layer 12, and then a photolithographic process is used to form a pattern on the silicon nitride layer 12. Then, the silicon nitride layer 12 is anisotropically etched to exposed portions of the pad oxide layer using a dry etching method. Similarly, using a photoresist layer 13 and photolithographic processing again, a pattern is formed on the pad oxide layer 11 and the substrate 10. Then, the exposed pad oxide layer 11 is anisotropically etched using a dry etching method. Etching continues down into the substrate 10, and finally forming a trench 14 having interior surfaces 15 that exposes portions of the substrate 10.
Next, as shown in FIG. 1C, the photoresist layer 13 is removed to expose the silicon nitride layer 12.
FIG. 2 is a magnified view showing the features at the corner within the dash circle of FIG. 1C. As shown in FIG. 2, the exposed substrate surface at the upper corner of the trench 14 is rather small. Furthermore, subsequently formed liner oxide layer will have a rather steep gradient along the trench corner location.
Thereafter, a liner oxide layer is formed at a high temperature using a thermal oxidation process. The liner oxide layer covers the interior surfaces 15 of the trench 14, and has contact with the pad oxide layer 11 at the upper corner of the trench 14.
Finally, conventional processes are performed to complete the structural formation of shallow trench isolation. For example, the trench 14 is filled using an insulating material such as silicon dioxide. Other subsequent processes are known to those skill in the art, therefore detail description is omitted here.
In the conventional method, the exposed substrate area at the upper trench corners is very small. Moreover, one side of the upper corner is the substrate, while the other side is the pad oxide layer. Therefore, the subsequently formed gate oxide layer will be thinner, thereby leading to a lowering of its reliability. Another consequence of a thin gate oxide layer is that there is an increase in the electric field strength at the upper corner locations. Furthermore, the upper corner fabricated by a conventional method is not too smooth either.
Moreover, due to the over-exposure of the substrate at the upper corner of the trench in a subsequent pad oxide layer removing process, kink effect is easily produced at the upper corner locations. Hence, sub-threshold current will be generated in the device, thereby leading to a current leakage problem.
In light of the foregoing, there is a need in the art to improve the method for manufacturing shallow trench isolation.